Researchers create programmable routers for data centre
Thu 25 Aug 2016
Researchers at MIT have created a programmable router chip that can be used to monitor and respond to changing data center traffic demands and network conditions in real time. This represents an enormous step in data center functionality and efficiency, replacing the current system of hard-wired algorithms with agile, responsive packet management that does not sacrifice speed.
The research team published two papers on programmable routers this week. The first outlines specs for seven progressively more complex circuit types. The circuit can be modified based on the complexity of the demands placed on it for traffic management – responding to different data requests, requiring different traffic speeds, queueing requests in order of urgency, and modifying acceptable ranges for packet loss within specific data loads are just some of the preferences controlled by router algorithms.
A bank of the least complex circuit outlined in the MIT paper would use only 0.16% of an available router chip; the most complex only 4%. This leaves ample room to manage the speed of data traffic, and for add-ons and experimentation with the new design.
Hari Balakrishnan, the Fujitsu Professor in Electrical Engineering and Computer Science at MIT said, “You need to have the ability for researchers and engineers to try out thousands of ideas. With this platform, you become constrained not by hardware or technological limitations, but by your creativity. You can innovate much more rapidly.”
The second paper outlines the design of the scheduler, which prioritizes and queues data packets that are processed through the router. The circuit designs and scheduler designs were written in Verilog, which has a built-in analytics tool that verified the circuits and schedulers could be deployed in a working data center without any loss of transmission speed.
In order to preserve the speed required to process the massive amounts of data in a data center, routers have had their traffic pattern analysis and packet management algorithms hard-wired directly in the router circuitry. Use of a new algorithm requires new hardware rather than a software patch. Programmable routers have been available before now, but until now were an unworkable solution because they represented a significant loss in speed – by a factor of 10 to a factor of 100, in some cases. A fully programmable router chip that allows a data center to maintain speed and functionality while responding to traffic demands and network conditions would represent a major step in creating a data center where equipment can evolve to match the demands placed on it.