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Samsung successfully develops 5nm semiconductor process

Written by Tue 16 Apr 2019

Korean chipmaker’s latest EUV innovation promises fresh performance boost and reduction in power consumption and size

In an era where Moore’s Law is already being pushed to the limit, the semiconductor industry is still churning out remarkable innovations in chip fabrication.

The latest innovation hails from Korean chipmaker Samsung, which this week announced it has developed a 5-nanometer (nm) semiconductor process using its extreme ultraviolet (EUV) technology.

For more than a decade, EUV has been hailed as the technology that will extend the lifespan of Moore’s Law. The process uses ultraviolet light to create billions of tiny structures on the thin slices of silicon that make up chips, enabling smaller, speedier and more powerful chips.

The announcement comes just a few months after Samsung began mass production of EUV-based processors using a 7nm process that it unveiled in October last year, mainly for use in its flagship smartphone models.

The rapid progress has been made possible in large part by running thousands of wafer layers through EUV exposure systems each week, revealed senior engineer Daewon Ha.

“Hands-on experience is the only way to ascend the EUV learning curve, and that body of knowledge is growing daily,” Ha said.

The chipmaker says the new 5nm process provides up to a 20 percent reduction in power consumption, a 10 percent performance boost, and a 25 percent reduction in chip size compared to 7nm. Samsung is expected to commercialise the process next year.

Samsung also announced that it is colloborating with customers on a 6nm process that will begin mass production this year.

Samsung is not the only chipmaker pushing the boundaries of fabrication. Rival TSMC is beginning 7nm EUV production for Apple’s A13 processor this quarter, and earlier this month announced it has started producing prototype 5nm chips.

Intel has only recently started manufacturing chips using a 10nm process, although it is able to squeeze in more transistors per nm.

Written by Tue 16 Apr 2019


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